The present invention relates to a semiconductor device and a method for fabricating the device, and in particular relates to a semiconductor device having an STI structure and a method for fabricating the device.
In recent years, as the packing density of a semiconductor integrated circuit is increased, shallow trench isolation (STI) is adopted as an isolation technique. In this technique, a shallow trench is provided in a substrate, and the trench is filled with an insulating film, thereby forming an isolation region. In the step of forming an STI structure, the insulating film deposited over the substrate is polished by chemical-mechanical polishing (CMP), for example. If the isolation region is large, in the CMP process, there occurs a phenomenon called “dishing” in which the insulating film in the trench is excessively polished; therefore, a method for defining a dummy pattern in an area except an active area is used. As an exemplary method for forming an isolation region as mentioned above, the method disclosed in Japanese Unexamined Patent Publication No. 2001-176959 is known. This method will be described below.
FIGS. 5A and 5B are cross-sectional views illustrating a part of a conventional method for fabricating a semiconductor device having an STI structure, and FIGS. 6A through 6C are cross-sectional views illustrating the conventional method for fabricating the semiconductor device.
First, as shown in FIG. 6A, an underlying oxide film 14 is formed on a semiconductor substrate 12 made of single-crystal silicon or the like, and then a nitride film 15 is formed on the underlying oxide film 14. Subsequently, the nitride film 15 is selectively removed except portions thereof in a device pattern 9 and dummy patterns 11, and thereafter the semiconductor substrate 12 and the underlying oxide film 14 are partially etched using the remaining nitride film 15 as a mask, thereby forming trenches 16. Herein, the “device pattern” refers to the pattern of an active area for forming a semiconductor element such as a MOSFET afterward. Further, the “dummy pattern” refers to the pattern, which is provided in an isolation region other than the active area, for preventing dishing, and includes a dummy active area. If a trench has a large width, the polishing of an insulating film that fills the trench proceeds at a higher rate than that of an insulating film that fills a trench having a narrow width. In this step, by defining the dummy patterns in a region where an insulating film for isolation should be originally formed, the occurrence of dishing can be suppressed in the subsequent CMP process.
Next, an oxide film is deposited over the substrate, thereby forming an HDP (High Density Plasma) oxide film 13 that fills at least the trenches 16. Herein, a portion of the HDP oxide film 13 located over the relatively large isolation region is defined as an “HDP oxide film 13a”, while a portion of the HDP oxide film 13 located over the minute active area is defined as an “HDP oxide film 13c”. Thereafter, a resist pattern 17 having a size larger than a predetermined pattern size is defined over the HDP oxide film 13 to etch away a portion of the HDP oxide film 13 formed over the dummy active area. This resist pattern 17 is defined so as to make an opening thereof smaller in size than the active area that is the target for etching, for example.
Then, as shown in FIG. 6B, using the resist pattern 17 as a mask, the etching of the HDP oxide film 13 is carried out to reach the nitride film 15 so that an opening is formed in the HDP oxide film 13. Thus, the HDP oxide film 13a is opened at its region located over the relatively large dummy active area, and only portions of the HDP oxide film 13a located above ends of the dummy active area remain (hereinafter, these remaining portions will be called “end portions 13b”). In this step, in order to allow the nitride film 15 to function as an etch stopper, the width of the opening has to be equal to or larger than a certain width. Therefore, the width of the dummy active area is preferably about 3 μm to about 10 μm, for example.
It should be noted that the HDP oxide film 13c formed over the minute device pattern 9 is formed into a small triangular shape as shown in FIG. 6B. For example, in a region where a plurality of the minute device patterns 9 are densely provided such as a memory cell section of a dynamic random-access memory (DRAM), a large number of the HDP oxide films 13c, each having a small triangular shape, are densely provided.
Subsequently, as shown in FIG. 6C, a CMP process is performed using, for example, a silica slurry to polish the HDP oxide film 13, thereby removing portions of the HDP oxide film 13 located on the nitride film 15. Thus, the HDP oxide film 13 remains only in the trenches 16, and oxide films 20 for trench isolation are formed.
Then, the nitride film 15 and the underlying oxide film 14 are sequentially removed by wet etching, thereby completing the isolation.
In the conventional semiconductor device fabricating method, the HDP oxide film 13a over a portion of the dummy active area having a large width is etched beforehand in the step shown in FIG. 6B. Thus, it is possible to reduce the amount of the HDP oxide film 13 over a dummy pattern region, which is to be polished in the step shown in FIG. 6C. As a result, the time required for the polishing can be reduced.